1. Field of the Invention
The present invention relates to adaptive calibration of capacitor values in a successive approximation analog-to-digital converter having a radix weighted multi-capacitor charge redistribution digital-to-analog converter (CRDAC), and more particularly to adaptive calibration of the capacitor values in the CRDAC, and systems and methods for adaptive, self-stimulated autocalibration in connection with digital-to-analog converter (DAC) auto-measurement in analog-to-digital (A/D) converters.
2. Description of the Related Art
One attempt to design a calibrated successive approximation architecture is described in David R. Welland""s U.S. Pat. No. 4,709,225 (granted in 1987). Binary weighting after wafer fabrication is set forth in the patent according to the Welland approach, which includes adjusting an array of capacitors scaled according to a radix 2 (i.e., binary) function, resulting in non-overlap.
Related art U.S. Pat. No. 4,336,526 granted to Basil Weir describes successive approximation analog-to-digital conversion (ADC) using a radix less than two weighted digital-to-analog converter (DAC) in a feedback loop using a comparator and a successive approximation register (SAR) logic circuit to solve the binary non-overlap problem. A proposed conversion operation produces a digital output representative of an unknown analog input. A DAC accepts a digital word comprising a sequence of series bits, to produce a corresponding analog voltage value. An impedance network is described including capacitors, for example, which have sequential capacitance values which are a function of radix less than two. Costly and complicated switching circuits precisely represent accurate series weights in such an impedance network. A first analog cancellation voltage is produced in the DAC with a selected most significant bit (MSB) capacitance. The first analog cancellation voltage is input to a comparator to set-off a received analog voltage which is to be converted into digital form by SAR conversion. If the first analog cancellation voltage from the MSB is insufficient to cancel out the received analog voltage under conversion, as evidenced by the sign of the output value from the comparator, then the tested MSB is kept. Unfortunately, Weir does not show or suggest adaptive calibration.
In a binary sequence network, the MSB capacitance in a selected impedance network of n capacitors slightly exceeds the sum of the remaining totality of less significant capacitances. Accordingly, if by virtue of noise or some other ancillary effect, a MSB is erroneously kept, then not even summing all the contributions from the remaining less significant capacitances will result in an approximation which has a cumulative value greater than the most significant capacitance. In other words, the use of radix 2 for successive approximation according to the prior art is technically disadvantageous, because for radix 2, there is no recovery from an erroneous (e.g., noise-induced) approximation with a particular most significant value bit, because the sum of the less significant bit capacitances or voltage figures does not reach either singly or cumulatively to the magnitude of the single erroneously kept voltage or capacitance level. Simply stated, with a radix 2 series, there is no redundancy which permits alternative expressions of particular voltage or capacitance levels.
According to the present invention, a system for adaptive auto-calibration of radix less than 2 A/D SAR converters with internally generated stimuli, includes a plurality of DAC elements having element values ratioed by radix less than 2 with respect to at least one other element, the values of said plurality of DAC elements being subject to calibration. The system further includes a memory for storing digital DAC element values; and a controller for determining values of said plurality of DAC elements for storage in said memory, based upon calibration operation using said DAC elements, and performing conversion of analog voltages into digital counterpart values, during conversion operation using calibration values of the DAC elements established during calibration and stored in the memory.
According to one embodiment of the present invention, a physically fixed set of capacitances is contructed as a tapered array for use without trimming or electronic adjustment, and a memory is trained to incrementally converge corresponding digital weights corresponding to the actual physical values of the constructed set of capacitances, permitting determination of unknown analog voltages by approximation with the constructed capacitances as reflected in corresponding digital weight values. According to the present invention, instead of physically or electrically adapting a constructed capacitor array, to establish a precise radix 2 tapered capacitor array, a digital weight array of values is constructed in register memory locations which is respectively representative of the actual constructed capacitor array values. This reduces manufacturing costs, because no precise capacitor array needs to be constructed. Instead, the actual capacitance ratios of a roughly constructed, non-precision capacitor array, are determined and stored in memory, to enable precise analog-to-digital conversion with an array of capacitors which are not precisely ratioed according to a predetermined radix value distribution.
According to one embodiment of the present invention, adaptive calibration of a charge redistribution digital-to-analog converter includes producing a set of sampling bits to connect sampling components such as capacitors or resistors to a selected reference voltage. Different sets of sampling bits are used to cover a selected calibration range, with the sampling sets being predetermined, fixed, random, or pseudo-random. Each set of sampling bits produces a corresponding sampled value. The sampled value is approximated with successive balancing values produced with corresponding sets of balancing bits. An analog residue is produced from the difference between the sampled and balancing values. Digital weights are generated corresponding to the sampling and balancing bits. A digital residue is determined from the difference between the sampling and balancing digital weights. The charge redistribution digital-to-analog converter includes a set of multi-valued components which can redundantly approximate particular sampled values. According to one embodiment of the present invention, the set of components includes capacitors which can be organized into subsets of capacitance values which can redundantly approximate desired capacitance values within a predetermined range.
According to the present invention, adaptive calibration is accomplished without an external impulse by a non-binary companion bit charge redistribution digital-to-analog SAR converter. Companion bits are selected lower significance bits used with associated test bits to choose particular capacitors during SAR processing and having a predetermined magnitude relationship with the test bits. Conversion of SAR capacitors according to the present invention includes balancing a sampled charge with a group of capacitors having capacitance values scaled according to a radix less-than-two function and including companion bit capacitors.